Method of depositing high-quality sige on sige substrates

ABSTRACT

This invention provides a method of depositing high-quality Si or SiGe epitaxial layers on SiGe substrates. By first depositing a thin Si seed layer on the SiGe substrate, the quality of the seed layer and of the subsequently deposited layers is greatly improved over what is obtained from depositing SiGe directly onto the SiGe substrate. Indeed, whereas the RMS surface roughness of the deposition of SiGe directly on SiGe, as measured by atomic-force microscopy (AFM), was 3-4 nm, it was more than an order of magnitude better when a thin Si seed layer was employed. This work was performed on an ultra-high-vacuum chemical vapor deposition (UHV/CVD) system; however, the same method would apply to other deposition systems such as atmospheric-pressure, low-pressure and rapid-thermal CVD.

FIELD OF THE INVENTION

This invention relates to the growth of silicon (Si) or SiGe (SiliconGermanium alloy) epitaxial layers on SiGe substrates.

BACKGROUND OF THE INVENTION

The introduction of silicon germanium (SiGe) epitaxial technology hasallowed GaAs high-frequency (microwave) transistors to be replaced withsilicon transistors in numerous applications. For example, whilestandard silicon bipolar transistors could not operate reliably above 1GHz, SiGe Heterostructure Bipolar Transistors (HBT) are now beginning toappear in circuits designed to operate above 10 GHz.

However, SiGe devices fabricated on Silicon (Si) substrates are subjectto a number of inherent restrictions. Due to the large lattice mismatchbetween silicon and germanium (Ge), an alloy SiGe layer grown on top ofa silicon substrate or single-crystal surface must remain below acertain critical thickness in order to prevent relaxation through theformation of threading dislocations. Such defects can propagate throughthe Si and SiGe layers and cause the devices fabricated using theselayers to experience high percentages of failure. Consequently, theoverall yield of such a fabrication process will be far lower than wouldgenerally be acceptable in comparison to rival fabrication technologies.

Thus, control of strain in Si and SiGe layers deposited on varioussemiconductor surfaces is a challenging area of development andimportant to the fabrication of devices and circuits. Specifically, thestrain in the epitaxial layer (i.e. the layer grown/deposited on thesubstrate) alters the electrical characteristics of the compositesemiconductor material. That is, various parameters such as electron andhole mobility, energy bandgap, etc. are known to change as a result of achange in the ‘built-in’ strain associated with matching the atomiclattice structure of the epitaxial layer with that of the layer (e.g.the substrate or another between layer) onto which the epitaxial layeris grown.

The lattice strain within the deposited or grown layers may alter thesusceptibility of the layers to various etching or dissolving solvents.In the construction of micro-mechanical devices (MEMS) strain in thedeposited or grown layers and the morphology of such layers areimportant variables in the device commercial fabrication and yield atwhich devices can be successfully reproduced.

The availability of high-quality SiGe substrates would permit thedevelopment of new devices with thicker, lattice-matched SiGe,tensile-strained Si or SiGe layers, or strain-compensated Si/SiGestructures. However, a SiGe substrate would typically have an atomicspacing (lattice constant) different from the epitaxial layer grown ontop of it; and, therefore growing a Si or SiGe epitaxial layer—with adifferent percentage of Ge—would induce different strain conditions.

Moreover, until recently, the only available SiGe substrates werevirtual SiGe substrates; these are actually Si substrates with a thick,relaxed SiGe buffer. However, the defect density of virtual SiGesubstrates is around 10⁴ cm⁻² which compared to single crystal siliconwafers is quite poor and, in the context of Silicon VLSI manufacturing,intolerable. In spite of this, good SiGe n-type (p-type) field-effecttransistors with relatively high electron (hole) mobility have beenrealized on these types of substrates.

The recent commercial introduction of single-crystal SiGe substratesmanufactured using the Czochralski technique, like their single crystalsilicon wafer counterparts, promises to further improve devicecharacteristics, percentage yield and to potentially allow forlarge-scale manufacturing of Si/SiGe FETs and HEMTs. These devices couldbe constructed on the aforementioned high-quality SiGe substrates havinga percentage yield acceptable to the general practices and coststructures of the Si VLSI industry. This would make possible, forexample, CMOS VLSI circuits, like those used in computer microprocessorsand memory chips, with increased speed of operation or lower powerconsumption than those without SiGe. Other potential applicationsinclude novel optoelectronic devices and Ge-based thermoelectricgenerators.

The pitfall, thus far, has been that the epitaxial deposition of SiGedirectly on SiGe substrates results in an interface between the twolayers that suffers from unacceptable strain conditions and poormorphology which in turn causes lattice defects within each of the twolayers; thereby significantly reducing the smoothness of the interface.Consequently, the epitaxial layer is of poor quality and uniformity,leading to a very rough surface morphology which in turn negativelyimpacts subsequent processing steps. It is now well established that thequality and performance of electronic devices is directly related to thesmoothness of interfaces between the substrate and the epitaxial layerand between layers; the smoother the interfaces, the better the devicesfabricated.

The problem of non-uniform growth or poor surface morphology (i.e.smoothness) may be compounded when growth of a SiGe epitaxial layer isto take place on a mixed-topology or patterned surface. For example, asurface with regions of oxide (silicon dioxide) and SiGe single crystalsurfaces will induce different growth rates for the SiGe epitaxial layeron the different surfaces which will in turn cause the grown (ordeposited) epitaxial layer to have a poor surface morphology.

Thus, there is a desire to provide a method of depositing high-qualitySi or SiGe epitaxial layers on SiGe substrates in which the surfaces ofthe deposited layers are substantially free of lattice defects and arethus substantially uniform. Moreover, it would be desirable for theinterfaces between the substrate and the deposited layers and betweenlayers to be smooth and substantially free of lattice defects.

SUMMARY OF THE INVENTION

According to a first aspect of the invention a method of depositing atleast one epitaxial layer of SiGe onto a SiGe substrate comprisingfirstly depositing on the SiGe substrate a thin Si seed layer and thendepositing on the Si seed layer the at least one epitaxial layer of SiGeis provided.

According to a second aspect the invention provides a method ofdepositing at least one epitaxial layer of Si onto a SiGe substratecomprising depositing on the SiGe substrate a thin Si seed layer andthen depositing on the Si seed layer the at least one epitaxial layer ofSi.

Moreover, for applications that require fully strained epitaxial layerswithout any dislocations care must be taken to ensure that the thicknessof the layer is below a certain critical thickness, whether the layer isSi or SiGe with a Ge percentage different from that of the substrate. Asnoted previously, above the critical thickness threading dislocationsmay be created that may potentially decrease the performance of devicesmade from such layers.

Another advantage of using a thin Si seed layer is its compatibilitywith growth on patterned substrates. A thin Si seed layer allowsconformal growth on substrates with varied topology (single-crystal andpolycrystalline Si, and silicon dioxide and nitride).

Advantageously, the method according to the invention may be used tofabricate active semiconductor devices, for example, HeterojunctionBipolar Transistors (HBT's).

Other aspects and features of the present invention will become apparentto those ordinarily skilled in the art upon review of the followingdescription of specific embodiments of the invention in conjunction withthe accompanying figures.

BRIEF DESCRIPTION OF THE DRAWING

The invention will now be described in greater detail with reference tothe accompanying diagram, in which:

FIG. 1 is a cross-sectional view illustrating an embodiment of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

This invention provides a method of depositing high-quality Si or SiGeepitaxial layers on SiGe substrates. By first depositing a thin Si seedlayer on the SiGe substrate, the quality of the seed layer and of thesubsequently deposited layers is greatly improved over what is obtainedfrom depositing SiGe directly onto the SiGe substrate. Indeed, whereasthe RMS surface roughness of the deposition of SiGe directly on SiGe, asmeasured by atomic-force microscopy (AFM), was 3-4 nm, it was more thanan order of magnitude better when a thin Si seed layer was employed.This work was performed on an ultra-high-vacuum chemical vapordeposition (UHV/CVD) system; however, the same method would apply toother deposition systems such as atmospheric-pressure, low-pressure andrapid-thermal CVD.

Specifically, referring to FIG. 1, on top of a SiGe substrate 10 thereis deposited a thin seed layer 12 of Si and on top of layer 12 there isdeposited a layer 12 of SiGe. For the purposes of the present inventionthe thin seed layer 12 of Si need only be of sufficient thickness tosubstantially coat the SiGe substrate surface and to provide asubstantially smooth surface onto which an epitaxial layer can bedeposited.

The SiGe substrate 10 is unstrained and has a low number of defects. Thepercentage of Ge in the SiGe substrate 10 is expressed as X % where0<X<100 and typically X=15.

With regard to the Si seed layer 12, it has a thickness t where10A<t<500A; typically t=100 Angstrom units.

For the SiGe layer 14, the percentage of Ge is expressed as Y % where0<Y<100 and typically Y=25. The SiGe layer 14 may be strained orunstrained and has a thickness t where 0 μm<t<25 μm; typically t=500Angstrom units, strained.

Although the invention is intended primarily to permit high qualityepitaxial deposition of SiGe on an SiGe substrate, the use of a thin Siseed layer can also be used to permit high quality epitaxial depositionof Si on an SiGe substrate. Moreover, the SiGe substrate may either havea SiGe single crystal surface or have a patterned surface made up ofexposed regions of SiGe and, for example, silicon dioxide (oxide).

While the preferred embodiment of the present invention has beendescribed and illustrated, it will be apparent to persons skilled in theart that numerous modifications and variations are possible.Specifically, the invention could be utilized to fabricate differentdevices of varying characteristics and performance. This could be doneby choosing the appropriate fractional Ge content X % of the SiGeepitaxial layer in relation to the fractional Ge content Y % of the SiGeSubstrate to achieve the desired effects. The choice of the amount ofGermanium in the epitaxial layers relative to the substrate effectivelyuses the strain (or lack thereof) inherent in the grown epitaxial layerto set the electrical qualities of the epitaxial layer.

For example, growing a 10% Ge SiGe epitaxial layer on 15% Ge SiGesubstrates means the grown SiGe epitaxial layer will be under stress,because the respective lattices are mismatched as a result of havedifferent percentages of germanium. The level of stress induced (as aresult of having the respective lattices mismatched) is used to alterthe electrical characteristics of the grown SiGe epitaxial layer.Moreover, by growing these layers using the Si seed layer method on SiGesubstrates not only does the quality of the grown epitaxial layersincreases dramatically, but so does the range of % Ge (i.e. percentgeranium) layers that can be grown effectively.

It would be appreciated by those skilled in the art that additionalepitaxial layers could be grown above the first epitaxial layer that hadbeen grown above the Si seed layer (with the Si seed layer grown abovethe SiGe substrate). Generally, a Si seed layer may be used to alleviatethe stress between two adjacent SiGe crystal layers that each have aunique percentage of Germanium (Ge) in relation to one another. Recall,it was discussed previously, that two SiGe crystals with differentamounts of Ge will suffer from strain at their interface due to therespective mismatched lattices of each. Clearly then, the invention isapplicable to the interface between epitaxial layers, each having adifferent percentage of Ge, in addition to the present embodiment inwhich a SiGe epitaxial layer is grown (deposited) above a SiGesubstrate. However, the invention is most advantageously employed whenonly a single Si seed layer is grown between a SiGe substrate and thefirst SiGe epitaxial layer and without using a Si seed layer between thefirst SiGe epitaxial layer and second SiGe layer, or between any othertwo epitaxial layers grown above the first SiGe layer.

Additionally, those skilled in the art would understand that anepitaxial layer grown above the Si seed layer provided by the inventionwould not necessarily have a uniform crystal structure. This couldpossibly occur if the Si seed layer is first deposited (grown) on top ofa patterned SiGe substrate. Recall that a patterned SiGe substrate wouldhave various exposed regions of SiGe (having a regular crystalstructure) and, for example, oxide (silicon dioxide). In the case wherethe epitaxial layer is grown over areas not having a regular crystalstructure the epitaxial layer is in danger of growing in the form ofmultiple small crystals (poly-crystalline material). In this instancethe Si seed layer will not necessary provide a single crystal growthsurface onto which an epitaxial layer can be deposited or grown. Rather,the Si seed layer simply provides a uniform (but not necessarily singlecrystal) surface upon which SiGe growth can “nucleate” equally overevery type of surface (single crystal or not).

Advantageously, other atomic elements may be incorporated into the grownepitaxial layer, or equivalently other atomic elements may be present ordeposited in the SiGe substrate. For example, those skilled in the artwould appreciate that various atomic elements are used for doping thesubstrate or grown epitaxial layers. In addition, it may be useful toincorporate Carbon or other atomic elements to control strain,diffusion, and a host of other material properties known to thoseskilled in the art. SiGe with carbon has already been seen in the priorart to control diffusion of boron and control strain. These types ofmodifications to the grown epitaxial layer or the substrate areconsidered to be within the scope and spirit of the present invention.

Furthermore, in addition to improving the quality of grown epitaxiallayers (both electrical and structural quality), the Si seed layer onSiGe substrates may also facilitate the reduction in time it takes togrow subsequent epitaxial layers. This is an important factor within thecontext of manufacturing.

Lastly, all methods and tools used for growing seed an epitaxial layerswill benefit from the present invention. Specifically, the invention isapplicable to the development of many different growth techniques beyondthe method of UHV-CVD including a new class of systems which use opticalor RF (Radio Frequency) plasma excitation of the growth surface.

1. A method of depositing at least one epitaxial layer of SiGe on to aSiGe substrate comprising firstly depositing on the SiGe substrate athin Si seed layer and then depositing on the Si seed layer theepitaxial layer of SiGe.
 2. A method according to claim 1, wherein thefraction of Ge, X %, within the SiGe substrate is different from thefraction of Ge, Y %, within the at least one SiGe epitaxial layer.
 3. Amethod according to claim 1, wherein the seed layer has a thickness10A<t<500A.
 4. A method according to claim 3, wherein t=substantially100A.
 5. A method according to claim 1, wherein the SiGe substrate hasexposed regions of SiGe and oxide and the seed layer is deposited on theexposed areas of SiGe and oxide.
 6. A method according to claim l,wherein the SiGe in the SiGe substrate is doped.
 7. A method accordingto claim 1, wherein the SiGe in the at least one SiGe epitaxial layer isdoped.
 8. A method of depositing at least one Si epitaxial layer onto aSiGe substrate comprising depositing on the SiGe substrate a thin Siseed layer and then depositing on the Si seed layer the at least one Siepitaxial layer.
 9. A device formed by the method of claim
 1. 10. Amethod according to claim 2, wherein the seed layer has a thickness10A<t<500A.
 11. A method according to claim 10, wherein t=substantially100A.
 12. A method according to claim 2, wherein the SiGe substrate hasexposed regions of SiGe and oxide and the seed layer is deposited on theexposed areas of SiGe and oxide.
 13. A method according to claim 3,wherein the SiGe substrate has exposed regions of SiGe and oxide and theseed layer is deposited on the exposed areas of SiGe and oxide.
 14. Amethod according to claim 4, wherein the SiGe substrate has exposedregions of SiGe and oxide and the seed layer is deposited on the exposedareas of SiGe and oxide.
 15. A method according to claim 2, wherein theSiGe in the SiGe substrate is doped.
 16. A method according to claim 3,wherein the SiGe in the SiGe substrate is doped.
 17. A method accordingto claim 2, wherein the SiGe in the at least one SiGe epitaxial layer isdoped.
 18. A method according to claim 3, wherein the SiGe in the atleast one SiGe epitaxial layer is doped.
 19. A device formed by themethod of claim
 2. 20. A device formed by the method of claim 8.